I. Field of the Invention
The present invention relates to a voltage controlled oscillator (VCO) circuit constructed in CMOS. More particularly, the present invention pertains to a CMOS VCO circuit wherein back gate CMOS terminals are employed for VCO tuning.
II. Description of Related Art
Oscillator circuits are well known and are employed in numerous applications. There are two primary types of VCO circuits; a relaxation type which employs a resistor-capacitor (RC) constant, and a resonant type which employs a tunable inductor-capacitor (LC) tank circuit. For high frequency applications, resonant tank circuits are preferred due to the frequency accuracy and reduced phase noise they exhibit, their stability and, perhaps most importantly, their high frequency capabilities.
Resonant oscillator circuits are formed from a parallel configuration of an inductance (L) and a capacitance (C). Under ideal conditions, such a parallel L-C arrangement will oscillate in perpetuity. However, due to resistance losses resulting from, inter alia, the inductance, the oscillation properties resemble an RLC circuit and result in a damping oscillation. Such an R-L-C circuit is shown in the prior art circuit of FIG. 1, wherein R represents the resistance losses in the circuit caused by the inductor L and capacitor C.
To eliminate the damping effect, the effect of resistance losses R must be cancelled, as for example shown in the circuit of FIG. 1b wherein a transconductance element (denoted as -R) is placed in parallel with the inductive losses R to cancel out the resistance. The equivalent schematic representation of FIG. 1b is shown in FIG. 1c wherein capacitor C is replaced by its equivalent, i.e. a pair of capacitors having equal value (2C). For tunability, the capacitors are replaced with variable capacitors, as seen in FIG. 1d.
As is known in the art, for VCO frequency stability the product of the L and C values must remain at a high constant value with a relatively large value inductor L used in combination with a small value capacitor. A large L is used for providing a robust oscillator i.e. to provide for ease in initiating oscillation of the circuit. It should, therefore, be recognized that if components having undesirably large parasitic capacitance values are used, then for a given LC value a lower value inductor will be required to compensate for the increased capacitance. A problem arises in VCO CMOS design because existing techniques for generating a transconductance element -R to compensate for the LC resistance loss results in relatively high parasitic capacitance. For example, and as shown in FIG. 2a, a CMOS N-channel transistor pair is employed to produce a transconductance effect. The circuit equivalent of FIG. 2a is shown in FIG. 2b wherein the CMOS transistor pair satisfactorily provides the transconductance element -R to compensate for the resistance loss inherent in the inductor. Such use of a CMOS transistor pair also undesirably produces an unwanted parasitic capacitance C' which, when incorporated in the circuit of FIG. 1d, results in the circuit of FIG. 3 wherein an N-channel CMOS pair and a P-channel CMOS pair are employed in a push-pull configuration for generating the large voltage swing for a low supply voltage. The arrangement of FIG. 3, however, disadvantageously exhibits a reduced tuning range and, as discussed above, an increased overall capacitance that dictates the use of a lower value inductor L to achieve a given LC constant.
The problem of parasitic capacitance is notably increased for high frequency VCO applications of 1 GHz and above, in which the integrated larger inductor L results in a larger R and, therefore, necessitates the use of larger transistors for a given supply voltage to generate a larger transconductance element (-R). The use of larger transistors, in turn, results in a higher parasitic capacitance.